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  1. Chuan MW, Riyadi MA, Hamzah A, Alias NE, Mohamed Sultan S, Lim CS, et al.
    PLoS One, 2022;17(3):e0264483.
    PMID: 35239699 DOI: 10.1371/journal.pone.0264483
    Moore's Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.
  2. Chuan MW, Wong KL, Riyadi MA, Hamzah A, Rusli S, Alias NE, et al.
    PLoS One, 2021;16(6):e0253289.
    PMID: 34125874 DOI: 10.1371/journal.pone.0253289
    Silicene has attracted remarkable attention in the semiconductor research community due to its silicon (Si) nature. It is predicted as one of the most promising candidates for the next generation nanoelectronic devices. In this paper, an efficient non-iterative technique is employed to create the SPICE models for p-type and n-type uniformly doped silicene field-effect transistors (FETs). The current-voltage characteristics show that the proposed silicene FET models exhibit high on-to-off current ratio under ballistic transport. In order to obtain practical digital logic timing diagrams, a parasitic load capacitance, which is dependent on the interconnect length, is attached at the output terminal of the logic circuits. Furthermore, the key circuit performance metrics, including the propagation delay, average power, power-delay product and energy-delay product of the proposed silicene-based logic gates are extracted and benchmarked with published results. The effects of the interconnect length to the propagation delay and average power are also investigated. The results of this work further envisage the uniformly doped silicene as a promising candidate for future nanoelectronic applications.
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