Molybdenum disulfide (MoS2) has distinctive electronic and mechanical properties which make it a highly prospective material for use as a channel in upcoming nanoelectronic devices. An analytical modeling framework was used to investigate the I-V characteristics of field-effect transistors based on MoS2. The study begins by developing a ballistic current equation using a circuit model with two contacts. The transmission probability, which considers both the acoustic and optical mean free path, is then derived. Next, the effect of phonon scattering on the device was examined by including transmission probabilities into the ballistic current equation. According to the findings, the presence of phonon scattering caused a decrease of 43.7% in the ballistic current of the device at room temperature when L = 10 nm. The influence of phonon scattering became more prominent as the temperature increased. In addition, this study also considers the impact of strain on the device. It is reported that applying compressive strain could increase the phonon scattering current by 13.3% at L = 10 nm at room temperature, as evaluated in terms of the electrons' effective masses. However, the phonon scattering current decreased by 13.3% under the same condition due to the existence of tensile strain. Moreover, incorporating a high-k dielectric to mitigate the impact of scattering resulted in an even greater improvement in device performance. Specifically, at L = 6 nm, the ballistic current was surpassed by 58.4%. Furthermore, the study achieved SS = 68.2 mV/dec using Al2O3 and an on-off ratio of 7.75 × 104 using HfO2. Finally, the analytical results were validated with previous works, showing comparable agreement with the existing literature.
Moore's Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.
Silicene has attracted remarkable attention in the semiconductor research community due to its silicon (Si) nature. It is predicted as one of the most promising candidates for the next generation nanoelectronic devices. In this paper, an efficient non-iterative technique is employed to create the SPICE models for p-type and n-type uniformly doped silicene field-effect transistors (FETs). The current-voltage characteristics show that the proposed silicene FET models exhibit high on-to-off current ratio under ballistic transport. In order to obtain practical digital logic timing diagrams, a parasitic load capacitance, which is dependent on the interconnect length, is attached at the output terminal of the logic circuits. Furthermore, the key circuit performance metrics, including the propagation delay, average power, power-delay product and energy-delay product of the proposed silicene-based logic gates are extracted and benchmarked with published results. The effects of the interconnect length to the propagation delay and average power are also investigated. The results of this work further envisage the uniformly doped silicene as a promising candidate for future nanoelectronic applications.