Affiliations 

  • 1 Department of Materials Science and Engineering, Yonsei University, Seoul 03722, South Korea
  • 2 Department of Electronic Materials Engineering, Kwangwoon University, Seoul 01897, South Korea
  • 3 Korea Institute of Science and Technology, KIST, Seoul 02792, South Korea
  • 4 Faculty of Engineering, Lincoln University College, Petaling Jaya, Selangor 47301, Malaysia
  • 5 Division of Electronic and Semiconductor Engineering, Ewha Womans University, Seoul 03760, South Korea
ACS Nano, 2024 Aug 15.
PMID: 39146081 DOI: 10.1021/acsnano.4c04316

Abstract

In this work, we report an n-type metal-oxide-semiconductor (nMOS) inverter using chemical vapor deposition (CVD)-grown monolayer WS2 field-effect transistors (FETs). Our large-area CVD-grown monolayer WS2 FETs exhibit outstanding electrical properties including a high on/off ratio, small subthreshold swing, and excellent drain-induced barrier lowering. These are achieved by n-type doping using AlOx/Al2O3 and a double-gate structure employing high-k dielectric HfO2. Due to the superior subthreshold characteristics, monolayer WS2 FETs show high transconductance and high output resistance in the subthreshold regime, resulting in significantly higher intrinsic gain compared to conventional Si MOSFETs. Therefore, we successfully realize subthreshold operating monolayer WS2 nMOS inverters with extremely high gains of 564 and 2056 at supply voltage (VDD) of 1 and 2 V, respectively, and low power consumption of ∼2.3 pW·μm-1 at VDD = 1 V. In addition, the monolayer WS2 nMOS inverter is further expanded to the demonstration of logic circuits such as AND, OR, NAND, NOR logic gates, and SRAM. These findings suggest the potential of monolayer WS2 for high-gain and low-power logic circuits and validate the practical application in large areas.

* Title and MeSH Headings from MEDLINE®/PubMed®, a database of the U.S. National Library of Medicine.