The reduction in the dimension of planar MOSFET device appears to be limited when it
reaches to 22nm technology node. In this research , a new concept of MOSFET architecture named
as Ultrathin Pillar Vertical Double Gate (VDG) MOSFET device was introduced and it was
integrated with silicon-on-insulator (SOI) technology for better electrical performances. The virtual
device fabrication and characterization were executed by using ATHENA and ATLAS modules from
SILVACO Internationals. The process parameters of the device were then optimized by utilizing the
Taguchi method for obtaining the lowest value of subthreshold swing (SS). The optimal result of the
subthreshold swing (SS) was observed to be 58.07 mV/dec with threshold voltage (VTH) of 0.408 V
and a very low leakage current (IOFF)value of 9.374 x 1016 A/µm. These results are well within the
predicted value of International Technology Roadmap Semiconductor (ITRS) 2013 for low power
(LP) requirement in the year 2020. Copyright © 2016 Penerbit Akademia Baru - All rights reserved.