This study explores optimization of resistance load (R-Load) of four silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. Noise margins and inflection voltage of butterfly characteristics with static power consumption of SRAM cell are used as limiting factors in this optimization. Range of R-Load used in this study was 20-1000 KΩ with Vdd = 1 V. Results indicate that optimization depends critically on resistance load value. The optimized range of R-Load is 100-200 KΩ.
This paper presents the temperature characteristics of silicon nanowire transistors (SiNWTs) and examines the effect of temperature on transfer characteristics, threshold voltage, I(ON)/I(OFF) ratio, drain-induced barrier lowering (DIBL), and sub-threshold swing (SS). The (MuGFET) simulation tool was used to investigate the temperature characteristics of a transistor. The findings reveal the negative effect of higher working temperature on the use of SiNWTs in electronic circuits, such as digital circuits and amplifiers circuits, because of the lower I(ON)/I(OFF) ratio, higher DIBL, and higher SS at higher temperature. Moreover, the ON state is the optimum condition for using a transistor as a temperature nano-sensor.
This paper shows the effect of the dimensions of nanowires on threshold voltage, ON/OFF current ratio, and sub-threshold slope. These parameters are critical factors of the characteristics of silicon nanowire transistors. The MuGFET simulation tool was used to investigate the characteristics of a transistor. Current-voltage characteristics with different dimensions were simulated. Results show that long nanowires with low diameter and oxide thickness tend to have the best transistor characteristics.
This study is the first to demonstrate dimensional optimization of nanowire-complementary metal-oxide-semiconductor inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on both dimensions ratio and digital voltage level (Vdd). Diameter optimization reveals that when Vdd increases, the optimized value of (Dp/Dn) decreases. Channel length optimization results show that when Vdd increases, the optimized value of Ln decreases and that of (Lp/Ln) increases. Dimension ratio optimization reveals that when Vdd increases, the optimized value of Kp/Kn decreases, and silicon nanowire transistor with suitable dimensions (higher Dp and Ln with lower Lp and Dn) can be fabricated.