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A time series based sequence prediction algorithm to detect activities of daily living in smart home

Marufuzzaman M, Reaz MB, Ali MA, Rahman LF

Methods Inf Med, 2015;54(3):262-70.
PMID: 25604028 DOI: 10.3414/ME14-01-0061

OBJECTIVES: The goal of smart homes is to create an intelligent environment adapting the inhabitants need and assisting the person who needs special care and safety in their daily life. This can be reached by collecting the ADL (activities of daily living) data and further analysis within existing computing elements. In this research, a very recent algorithm named sequence prediction via enhanced episode discovery (SPEED) is modified and in order to improve accuracy time component is included.
METHODS: The modified SPEED or M-SPEED is a sequence prediction algorithm, which modified the previous SPEED algorithm by using time duration of appliance's ON-OFF states to decide the next state. M-SPEED discovered periodic episodes of inhabitant behavior, trained it with learned episodes, and made decisions based on the obtained knowledge.
RESULTS: The results showed that M-SPEED achieves 96.8% prediction accuracy, which is better than other time prediction algorithms like PUBS, ALZ with temporal rules and the previous SPEED.
CONCLUSIONS: Since human behavior shows natural temporal patterns, duration times can be used to predict future events more accurately. This inhabitant activity prediction system will certainly improve the smart homes by ensuring safety and better care for elderly and handicapped people.
Fulltext High-speed current dq PI controller for vector controlled PMSM drive

Marufuzzaman M, Reaz MB, Rahman LF, Chang TG

ScientificWorldJournal, 2014;2014:709635.
PMID: 24574913 DOI: 10.1155/2014/709635

High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Current dq controller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed current dq PI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era.
Fulltext Traceability of Sustainability and Safety in Fishery Supply Chain Management Systems Using Radio Frequency Identification Technology

Rahman LF, Alam L, Marufuzzaman M, Sumaila UR

Foods, 2021 Sep 24;10(10).
PMID: 34681313 DOI: 10.3390/foods10102265

At present, sustainability and emerging technology are the main issues in any supply chain management (SCM) sector. At the same time, the ongoing pandemic is increasing consumers' concerns about food safety, processing, and distribution, which should meet sustainability requirements. Thus, supervision and monitoring of product quality with symmetric information traceability are important in fresh food and fishery SCM. Food safety and traceability systems based on blockchain, Internet of Things (IoT), wireless sensor networks (WSN), and radio frequency identification (RFID) provide reliability from production to consumption. This review focuses on RFID-based traceability systems in fisheries' SCM, which have been employed globally to ensure fish quality and security, and summarizes their advantages in real-time applications. The results of this study will help future researchers to improve consumers' trust in fisheries SCM. Thus, this review aims to provide guidelines and solutions for enhancing the reliability of RFID-based traceability in food SCM systems so to ensure the integrity and transparency of product information.
Fulltext A high-speed and low-offset dynamic latch comparator

Rahman LF, Bin Ibne Reaz M, Yin CC, Marufuzzaman M, Rahman MA

ScientificWorldJournal, 2014;2014:258068.
PMID: 25114959 DOI: 10.1155/2014/258068

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 μm × 59.70 μm.
Fulltext Design of high speed and low offset dynamic latch comparator in 0.18 µm CMOS process

Rahman LF, Reaz MB, Yin CC, Ali MA, Marufuzzaman M

PLoS One, 2014;9(10):e108634.
PMID: 25299266 DOI: 10.1371/journal.pone.0108634

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.
Fulltext A low power and low ripple CMOS high voltage generator for RFID transponder EEPROM

Rahman LF, Marufuzzaman M, Alam L, Sidek LM, Reaz MBI

PLoS One, 2020;15(2):e0225408.
PMID: 32023244 DOI: 10.1371/journal.pone.0225408

A high-voltage generator (HVG) is an essential part of a radio frequency identification electrically erasable programmable read-only memory (RFID-EEPROM). An HVG circuit is used to generate a regulated output voltage that is higher than the power supply voltage. However, the performance of the HVG is affected owing to the high-power dissipation, high-ripple voltage and low-pumping efficiency. Therefore, a regulator circuit consists of a voltage divider, comparator and a voltage reference, which are respectively required to reduce the ripple voltage, increase pumping efficiency and decrease the power dissipation of the HVG. Conversely, a clock driving circuit consists of the current-starved ring oscillator (CSRO), and the non- overlapping clock generator is required to drive the clock signals of the HVG circuit. In this study, the Mentor Graphics EldoSpice software package is used to design and simulate the HVG circuitry. The results showed that the designed CSRO dissipated only 4.9 μW at 10.2 MHz and that the phase noise was only -119.38 dBc/Hz at 1 MHz. Moreover, the proposed charge pump circuit was able to generate a maximum VPP of 13.53 V and it dissipated a power of only 31.01 μW for an input voltage VDD of 1.8 V. After integrating all the HVG modules, the results showed that the regulated HVG circuit was also able to generate a higher VPP of 14.59 V, while the total power dissipated was only 0.12 mW with a chip area of 0.044 mm2. Moreover, the HVG circuit produced a pumping efficiency of 90% and reduced the ripple voltage to <4 mV. Therefore, the integration of all the proposed modules in HVG ensured low-ripple programming voltages, higher pumping efficiency, and EEPROMs with lower power dissipation, and can be extensively used in low-power applications, such as in non-volatile memory, radiofrequency identification transponders, on-chip direct current DC-DC converters.