Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

Abdulrazzaq BI 1 , Ibrahim OJ 2 , Kawahito S 3 , Sidek RM 4 , Shafie S 5 , Yunus NA 6 Show all authors , Lee L 7 , Halin IA 8

Affiliations 

  • 1 Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia. bilal.i.abdulrazzaq@gmail.com
  • 2 Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia. omar.j.ibrahim@gmail.com
  • 3 Imaging Devices Laboratory, Research Institute of Electronics, Shizuoka University, 3-5-1 Johoku, Nakaku, Hamamatsu, Shizuoka 432-8011, Japan. kawahito@idl.rie.shizuoka.ac.jp
  • 4 Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia. roslinams@upm.edu.my
  • 5 Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia. suhaidi@upm.edu.my
  • 6 Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia. amziah@upm.edu.my
  • 7 Faculty of Engineering, Multimedia University, Persiaran Multimedia, Cyberjaya 63100, Malaysia. linilee@mmu.edu.my
  • 8 Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia. izhal@upm.edu.my
Sensors (Basel), 2016 Sep 28;16(10).
PMID: 27690040

Abstract

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL's internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 µm Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture's circuit is 0.1 mW when the DLL is operated at 2 GHz.

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