With the advancement of digital microfluidics technology, applications such as on-chip DNA analysis, point of care diagnosis and automated drug discovery are common nowadays. The use of Digital Microfluidics Biochips (DMFBs) in disease assessment and recognition of target molecules had become popular during the past few years. The reliability of these DMFBs is crucial when they are used in various medical applications. Errors found in these biochips are mainly due to the defects developed during droplet manipulation, chip degradation and inaccuracies in the bio-assay experiments. The recently proposed Micro-electrode-dot Array (MEDA)-based DMFBs involve both fluidic and electronic domains in the micro-electrode cell. Thus, the testing techniques for these biochips should be revised in order to ensure proper functionality. This paper describes recent advances in the testing technologies for digital microfluidics biochips, which would serve as a useful platform for developing revised/new testing techniques for MEDA-based biochips. Therefore, the relevancy of these techniques with respect to testing of MEDA-based biochips is analyzed in order to exploit the full potential of these biochips.
Accurate detection of diabetic retinopathy (DR) mainly depends on identification of retinal landmarks such as optic disc and fovea. Present methods suffer from challenges like less accuracy and high computational complexity. To address this issue, this paper presents a novel approach for fast and accurate localization of optic disc (OD) and fovea using one-dimensional scanned intensity profile analysis. The proposed method utilizes both time and frequency domain information effectively for localization of OD. The final OD center is located using signal peak-valley detection in time domain and discontinuity detection in frequency domain analysis. However, with the help of detected OD location, the fovea center is located using signal valley analysis. Experiments were conducted on MESSIDOR dataset, where OD was successfully located in 1197 out of 1200 images (99.75%) and fovea in 1196 out of 1200 images (99.66%) with an average computation time of 0.52s. The large scale evaluation has been carried out extensively on nine publicly available databases. The proposed method is highly efficient in terms of quickly and accurately localizing OD and fovea structure together compared with the other state-of-the-art methods.
Industrialization has led to a huge demand for a network control system to monitor and control multi-loop processes with high effectiveness. Due to these advancements, new industrial wireless sensor network (IWSN) standards such as ZigBee, WirelessHART, ISA 100.11a wireless, and Wireless network for Industrial Automation-Process Automation (WIA-PA) have begun to emerge based on their wired conventional structure with additional developments. This advancement improved flexibility, scalability, needed fewer cables, reduced the network installation and commissioning time, increased productivity, and reduced maintenance costs compared to wired networks. On the other hand, using IWSNs for process control comes with the critical challenge of handling stochastic network delays, packet drop, and external noises which are capable of degrading the controller performance. Thus, this paper presents a detailed study focusing only on the adoption of WirelessHART in simulations and real-time applications for industrial process monitoring and control with its crucial challenges and design requirements.
Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option. CNTFETs are currently being preferred for implementing ternary circuits due to their desirable multiple threshold voltage and geometry-dependent properties, whereas the RRAM is used due to its multilevel cell capability which enables storage of multiple resistance states within a single cell. This article presents the 2-trit arithmetic logic unit (ALU) design using CNTFETs and RRAM as the design elements. The proposed ALU incorporates a transmission gate block, a function select block, and various ternary function processing modules. The ALU design optimization is achieved by introducing a controlled ternary adder-subtractor module instead of separate adder and subtractor circuits. The simulations are analyzed and validated using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions (supply voltages) to test the robustness of the designs. The simulation results indicate that the proposed CNTFET-RRAM integration enables the compact circuit realization with good robustness. Moreover, due to the addition of RRAM as circuit element, the proposed ALU has the advantage of non-volatility.
The modern-day computing technologies are continuously undergoing a rapid changing landscape; thus, the demands of new memory types are growing that will be fast, energy efficient and durable. The limited scaling capabilities of the conventional memory technologies are pushing the limits of data-intense applications beyond the scope of silicon-based complementary metal oxide semiconductors (CMOS). Resistive random access memory (RRAM) is one of the most suitable emerging memory technologies candidates that have demonstrated potential to replace state-of-the-art integrated electronic devices for advanced computing and digital and analog circuit applications including neuromorphic networks. RRAM has grown in prominence in the recent years due to its simple structure, long retention, high operating speed, ultra-low-power operation capabilities, ability to scale to lower dimensions without affecting the device performance and the possibility of three-dimensional integration for high-density applications. Over the past few years, research has shown RRAM as one of the most suitable candidates for designing efficient, intelligent and secure computing system in the post-CMOS era. In this manuscript, the journey and the device engineering of RRAM with a special focus on the resistive switching mechanism are detailed. This review also focuses on the RRAM based on two-dimensional (2D) materials, as 2D materials offer unique electrical, chemical, mechanical and physical properties owing to their ultrathin, flexible and multilayer structure. Finally, the applications of RRAM in the field of neuromorphic computing are presented.
This paper proposes a novel hybrid arithmetic-trigonometric optimization algorithm (ATOA) using different trigonometric functions for complex and continuously evolving real-time problems. The proposed algorithm adopts different trigonometric functions, namely sin, cos, and tan, with the conventional sine cosine algorithm (SCA) and arithmetic optimization algorithm (AOA) to improve the convergence rate and optimal search area in the exploration and exploitation phases. The proposed algorithm is simulated with 33 distinct optimization test problems consisting of multiple dimensions to showcase the effectiveness of ATOA. Furthermore, the different variants of the ATOA optimization technique are used to obtain the controller parameters for the real-time pressure process plant to investigate its performance. The obtained results have shown a remarkable performance improvement compared with the existing algorithms.
Wireless mesh networks (WMNs) play a vital role in modern communication systems, and optimizing the placement of wireless mesh routers is crucial for achieving efficient network performance in terms of coverage and connectivity. However, network congestion caused by overlapping routers poses challenges in WMN optimization. To address these issues, researchers have explored metaheuristic algorithms to strike a balance between coverage and connectivity in WMNs. This study introduces a novel hybrid optimization algorithm, namely Transient Trigonometric Harris Hawks Optimizer (TTHHO), specifically designed to tackle the optimization problems in WMNs. The primary objective of TTHHO is to find an optimal placement of routers that maximizes network coverage and ensures full connectivity among mesh routers. Notably, TTHHO's unique advantage lies in its efficient utilization of residual energy, strategically placing the sink node in areas with higher energy levels. The effectiveness of TTHHO is demonstrated through a comprehensive comparison with seven well-known algorithms, including Harris Hawks optimization (HHO), Sine Cosine Algorithm (SCA), Gray Wolf Optimization (GWO), Particle Swarm Optimization (PSO), Moth Flame Optimization (MFO), Equilibrium Optimizer (EO), and Transient Search Optimizer (TSO). The proposed algorithm is rigorously validated using 33 benchmark functions, and statistical analyses and simulation results confirm its superiority over other algorithms in terms of network connectivity, coverage, congestion reduction, and convergence. The simulation outcomes demonstrate the effectiveness and efficacy of the proposed TTHHO algorithm in optimizing WMNs, making it a promising approach for enhancing the performance of wireless communication systems.
The rapid advancement of new technologies has resulted in a surge of data, while conventional computers are nearing their computational limits. The prevalent von Neumann architecture, where processing and storage units operate independently, faces challenges such as data migration through buses, leading to decreased computing speed and increased energy loss. Ongoing research aims to enhance computing capabilities through the development of innovative chips and the adoption of new system architectures. One noteworthy advancement is Resistive Random Access Memory (RRAM), an emerging memory technology. RRAM can alter its resistance through electrical signals at both ends, retaining its state even after power-down. This technology holds promise in various areas, including logic computing, neural networks, brain-like computing, and integrated technologies combining sensing, storage, and computing. These cutting-edge technologies offer the potential to overcome the performance limitations of traditional architectures, significantly boosting computing power. This discussion explores the physical mechanisms, device structure, performance characteristics, and applications of RRAM devices. Additionally, we delve into the potential future adoption of these technologies at an industrial scale, along with prospects and upcoming research directions.