Silicon nanostructures have successfully been synthesized by thermal evaporation technique using nickel catalyst. Silicon powder served as starting source material was evaporated at high temperature (900-1100°C) in inert carrier gas. The grown silicon nanostructures were collected on (111) silicon substrate surface that positioned at varied location from source material. By controlling heating rate, gas flow rate, growth temperature and time, substrate position and location; to the optimum condition produced the best quality at silicon nanostructures. In this work, the best parameter to produce silicon nanostructures is system ramping up 1000°C at 20°C/min heating rate, N2 flow at 100ml/min; silicon needle-like one dimensional silicon nanostructures growth on vertically-positioned substrate located at 12cm from source material for 1 hour growth time. The effects of these parameters on the structures and physical of nanostructures were characterized by field emission scanning electron microscope and x-ray diffraction.
CaCu3Ti4O12 (CCTO) has attracted a great attention for electronic devices miniaturization due to its
very high dielectric constant properties at a wide range of frequency and nearly constant over broad temperature range. The origins of the giant dielectric constant have been speculated from electrical heterogeneous of interior elements of the CCTO ceramics. Four origins were suggested contributed to the electrical heterogeneous. In this study heat treatment were done with the electrode contact in Argon gas environment and the electrical properties over very wide frequency of CCTO ceramics were investigated. Cylindrical CCTO pellets samples were prepared by solid state reaction method and single phase of XRD pattern was obtained after sintering processes. Electrical impedance responds were measured at frequency from 100 Hz to 1 GHz for the samples for untreated and heat treated at 200ºC, 250ºC, 300ºC, 350ºC and 400ºC of CCTO. Improvement to the dielectric constant can be seen for 350ºC and 400ºC samples and dielectric loss were improved for 200ºC and 300ºC samples for overall frequency. The variations were discussed based on oxygen deficiency content and resistivity of the elements inside of CCTO structure.
Silicon nanowires were synthesized on Si substrates (111) via thermal evaporation using AuPd thin layer catalyst. Pre cleaned of Si wafer was used as a substrate to assemble the nanostructure products. In this work, the effect of growth temperature that ranging from 800 to 1000°C on the formation of silicon nanowires studied extensively. X-ray diffraction and field emission scanning electron microscope were employed to characterize the structures and morphology of nanowires. Vertical aligned silicon nanowires have been successfully grown on Si substrates at 900 and 1000°C. At 1100°C, the high aspect ratio of silicon nanowires can be produced but the formation density is low. The presence of AuPd catalyst on the tip of nanowires, it is expected that VLS is the most suitable to explain the growth mechanism of obtained SiNWs. The crystalline structure of SiNWs was proved by XRD data.
One-dimensional nanostructure materials are very attractive because of their electronic and optical properties depending on their size. It is well known that properties of material can be tuned by reducing size to nanoscale because at the small sizes, that they behave differently with its bulk materials and the band gap will control by the size. The tunability of the band gap makes nanostructured materials useful for many applications. As one of the wide band gaps semiconductor compounds, zinc selenide (ZnSe) nanostructures (nanoparticles, nanowires, nanorods) have received much attention for the application in optoelectronic devices, such as blue laser diode, light emitting diodes, solar cells and IR optical windows. In this study, ZnSe nanostructures have been synthesized by reduction process of zinc selenate using hydrazine hydrate (N2H4.2H2O). The reductive agent of hydrazine hydrate was added to the starting materials of zinc selenate were heat treated at 500 o C for 1 hour under argon flow to form onedimensional nanostructures. The SEM and TEM images show the formation of nanocompositelike structures, which some small nanobars and nanopellets stick to the rod. The x-ray diffraction and elemental composition analysis confirm the formation of mixture zinc oxide and zinc selenide phases.
P-type transparent conductive oxide of copper aluminum oxide (CuAlO2) thin films were prepared by using sol-gel method with nitrate solutions as starting precursor. Copper nitrate and aluminum nitrate were selected as raw materials that provide the copper and aluminum source. The CuAlO2 thin films were deposited on pre-cleaned silicon substrate by spin-coating technique. To study of phase formation of CuAlO2, as prepared sample was dried and subjected to heat treatment at various temperatures. The heat-treated samples were characterized by x-ray diffraction (XRD) and energy dispersive x-ray (EDX). From XRD analysis result found that CuAlO2 phase was formed after annealing at 1100 o C for 4 hrs. EDX result of annealed sample at 1100 o C shows composition of Cu and Al that indicate the possibility of forming CuAlO2.
This paper presents the effects of calcination time and sintering temperature on the properties of CaCu(3)Ti(4)O(12). Electroceramic material of CaCu(3)Ti(4)O(12) was prepared using a modified mechanical alloying technique that covers several processes, which are preparation of raw material, mixing and ball milling for 5 hours, calcination, pellet forming and, sintering. The objective of this modified technique is to enable the calcination and sintering processes to be carried out at a shorter time and lower temperature. The x-ray diffraction (XRD) analysis result shows that a single-phase of CaCu(3)Ti(4)O(12) was completely formed by calcination at 750 degrees C for 12 hours. Meanwhile, the grain size of a sample sintered at 1050 degrees C for 24 hours is extremely large, in the range of 20-50 mum obtained from field emission scanning electron microscopy (FESEM) images. The dielectric constant value of 14,635 was obtained at 10 kHz by impedance (LCR) meter in the sintered sample at 1050 degrees C. However, the dielectric constant value of samples sintered at 900 and 950 degrees C is quite low, in the range of 52-119.
Silicon nanowires (SiNWs) were fabricated by the electroless etching of an n-type Si (100) wafer in HF/AgNO3. Vertically aligned and high-density SiNWs are formed on the Si substrates. Various shapes of SiNWs are observed, including round, rectangular, and triangular. The recorded maximum reflectance of the SiNWs is approximately 19.2%, which is much lower than that of the Si substrate (65.1%). The minimum reflectance of the SiNWs is approximately 3.5% in the near UV region and 9.8% in the visible to near IR regions. The calculated band gap energy of the SiNWs is found to be slightly higher than that of the Si substrate. The I-V characteristics of a freestanding SiNW show a linear ohmic behavior for a forward bias up to 2.0 V. The average resistivity of a SiNW is approximately 33.94 Ω cm.
The junctionless nanowire transistor is a promising alternative for a new generation of nanotransistors. In this letter the atomic force microscopy nanolithography with two wet etching processes was implemented to fabricate simple structures as double gate and single gate junctionless silicon nanowire transistor on low doped p-type silicon-on-insulator wafer. The etching process was developed and optimized in the present work compared to our previous works. The output, transfer characteristics and drain conductance of both structures were compared. The trend for both devices found to be the same but differences in subthreshold swing, 'on/off' ratio, and threshold voltage were observed. The devices are 'on' state when performing as the pinch off devices. The positive gate voltage shows pinch off effect, while the negative gate voltage was unable to make a significant effect on drain current. The charge transmission in devices is also investigated in simple model according to a junctionless transistor principal.
A double-lateral-gate p-type junctionless transistor is fabricated on a low-doped (10(15)) silicon-on-insulator wafer by a lithography technique based on scanning probe microscopy and two steps of wet chemical etching. The experimental transfer characteristics are obtained and compared with the numerical characteristics of the device. The simulation results are used to investigate the pinch-off mechanism, from the flat band to the off state. The study is based on the variation of the carrier density and the electric-field components. The device is a pinch-off transistor, which is normally in the on state and is driven into the off state by the application of a positive gate voltage. We demonstrate that the depletion starts from the bottom corner of the channel facing the gates and expands toward the center and top of the channel. Redistribution of the carriers due to the electric field emanating from the gates creates an electric field perpendicular to the current, toward the bottom of the channel, which provides the electrostatic squeezing of the current.
In this letter, we investigate the fabrication of Silicon nanostructure patterned on lightly doped (10(15) cm(-3)) p-type silicon-on-insulator by atomic force microscope nanolithography technique. The local anodic oxidation followed by two wet etching steps, potassium hydroxide etching for silicon removal and hydrofluoric etching for oxide removal, are implemented to reach the structures. The impact of contributing parameters in oxidation such as tip materials, applying voltage on the tip, relative humidity and exposure time are studied. The effect of the etchant concentration (10% to 30% wt) of potassium hydroxide and its mixture with isopropyl alcohol (10%vol. IPA ) at different temperatures on silicon surface are expressed. For different KOH concentrations, the effect of etching with the IPA admixture and the effect of the immersing time in the etching process on the structure are investigated. The etching processes are accurately optimized by 30%wt. KOH +10%vol. IPA in appropriate time, temperature, and humidity.